Computer Architecture

Memory Hierarchy

This guide helps you get your bearings in Memory Hierarchy before you start exploring the interactive timeline, framework graph, and concept maps.

Before You Dive In

Memory Hierarchy focuses on how hardware organization determines real program performance and efficiency.
Rough timeline: scalar pipelines -> superscalar and out-of-order execution -> multicore and heterogeneous accelerators -> domain-specific hardware for ML and data workloads.
Start with the memory hierarchy and instruction-level parallelism; they dominate practical speedups.
In Noosaga, compare frameworks by bottleneck assumptions: compute bound, memory bound, or communication bound.

PipelineExecution structure dividing instruction processing into staged operations.

Cache hierarchyLayered memory system balancing latency, capacity, and bandwidth.

Out-of-order executionHardware scheduling that reorders instruction execution while preserving correctness.

Branch predictionSpeculative mechanism estimating control flow to keep pipelines full.

ISAInstruction set architecture: software-visible contract between hardware and compiler.

Assuming clock speed alone predicts performance across workloads.

Treating peak FLOPS as a universal metric independent of memory and data movement costs.

Confusing microarchitecture optimizations with ISA-level portability guarantees.

Open the interactive view and scan the framework timeline. Which frameworks came first? Which ones overlap? Where are the big transitions?

Click into individual frameworks to read what each one claims, where it came from, and how it relates to its neighbors.

See how the key ideas within a framework connect. This is useful for figuring out what to learn first and what depends on what.

Take the quiz for any framework you've read about. It's a quick way to find out whether you actually understood the core ideas or just skimmed them.